HD6417750 Datasheet, PDF (630/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 14.13 Register Configuration (cont)
Chan-
nel Name
Abbre-
viation
Read/
Area 7
Write Initial Value P4 Address Address
Access
Size
4
DMA source
SAR4
R/W Undefined H'FFA00050 H'1FA00050 32
address register 4
DMA destination DAR4
address register 4
R/W Undefined H'FFA00054 H'1FA00054 32
DMA transfer
count register 4
DMATCR4 R/W Undefined H'FFA00058 H'1FA00058 32
DMA channel
CHCR4
control register 4
R/W*¹ H'00000000 H'FFA0005C H'1FA0005C 32
5
DMA source
SAR5
R/W Undefined H'FFA00060 H'1FA00060 32
address register 5
DMA destination DAR5
address register 5
R/W Undefined H'FFA00064 H'1FA00064 32
DMA transfer
count register 5
DMATCR5 R/W Undefined H'FFA00068 H'1FA00068 32
DMA channel
CHCR5
control register 5
R/W*¹ H'00000000 H'FFA0006C H'1FA0006C 32
6
DMA source
SAR6
R/W Undefined H'FFA00070 H'1FA00070 32
address register 6
DMA destination DAR6
address register 6
R/W Undefined H'FFA00074 H'1FA00074 32
DMA transfer
count register 6
DMATCR6 R/W Undefined H'FFA00078 H'1FA00078 32
DMA channel
CHCR6
control register 6
R/W*¹ H'00000000 H'FFA0007C H'1FA0007C 32
7
DMA source
SAR7
R/W Undefined H'FFA00080 H'1FA00080 32
address register 7
DMA destination DAR7
address register 7
R/W Undefined H'FFA00084 H'1FA00084 32
DMA transfer
count register 7
DMATCR7 R/W Undefined H'FFA00088 H'1FA00088 32
DMA channel
CHCR7
control register 7
R/W*¹ H'00000000 H'FFA0008C H'1FA0008C 32
Notes: Longword access should be used for all control registers. If a different access width is
used, reads will return all 0s and writes will not be possible.
*1 Bit 1 of CHCR0–CHCR7 and bits 2 and 1 of DMAOR can only be written with 0 after
being read as 1, to clear the flags.
*2 In the SH7750R, writes from the CPU and writes from external I/O devices using the
DTR format are possible in DDT mode.
Rev. 6.0, 07/02, page 578 of 986