HD6417750 Datasheet, PDF (366/1039 Pages) Renesas Technology Corp – SuperH RISC engine

13.1.3 Pin Configuration
Table 13.1 shows the BSC pin configuration.
Table 13.1 BSC Pins
Name
Signals
I/O Description
Address bus
A25–A0
O
Address output
Data bus
D63–D52,
D31–D0
I/O Data input/output
When port functions are used and DDT mode is
selected, input the DTR format. Otherwise, when
port functions are used, D60-D52 cannot be used
and should be left open.
Data bus/port
D51–D32/
PORT19–
PORT0
I/O When port functions are not used: data input/output
When port functions are used: input/output port
(input or output set for each bit by register)
Bus cycle start %6
O
Signal that indicates the start of a bus cycle
When setting synchronous DRAM interface:
asserted once for a burst transfer
For other burst transfers: asserted each data cycle
Chip select 6–0 &69–&63
O
Chip select signals that indicate the area being
accessed
&68 and &69 are also used as PCMCIA &(4$ and
&(4%
Read/write
RD/:5
O
Data bus input/output direction designation signal
Also used as the DRAM/synchronous
DRAM/PCMCIA interface write designation signal
Row address
strobe
5$6
O
5$6 signal when setting DRAM/synchronous DRAM
interface
Read/column
5'/&$66/
O
Strobe signal that indicates a read cycle
address strobe/
cycle frame
)5$0(
When setting synchronous DRAM interface: &$6
signal
When setting MPX interface: )5$0( signal
Data enable 0
:(3/&$63/ O
DQM0
When setting synchronous DRAM interface:
selection signal for D7–D0
When setting DRAM interface: &$6 signal for
D7–D0
When setting MPX interface: high-level output
In other cases: write strobe signal for D7–D0
Rev. 6.0, 07/02, page 314 of 986