HD6417750 Datasheet, PDF (548/1039 Pages) Renesas Technology Corp – SuperH RISC engine

14.2 Register Descriptions (SH7750, SH7750S)
14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)
Bit: 31
30
29
28
27
26
25
24
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
0
·············································
Initial value: — · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · —
R/W: R/W · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · R/W
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that
specify the source address of a DMA transfer. These registers have a counter feedback function,
and during a DMA transfer they indicate the next source address. In single address mode, the SAR
value is ignored when an external device with DACK has been specified as the transfer source.
Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64-
bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will
be detected and the DMAC will halt.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode and deep sleep mode.
When transfer is performed from memory to an external device with DACK in DDT mode, DTR
format [31:0] is set in SAR0 [31:0]. For details, see Data Transfer Request Format in section
14.5.2.
In the SH7750, writes from the CPU are masked in DDT mode, while writes from external I/O
devices using the DTR format are possible. In the SH7750S, writes from the CPU and writes from
external I/O devices using the DTR format are possible In DDT mode.
Rev. 6.0, 07/02, page 496 of 986