 English |
|
|
|
|
|
|
|
| HD6417750 Datasheet, PDF (527/1039 Pages) Renesas Technology Corp – SuperH RISC engine | |||
| |||
| ◁ |
CKIO
A25âA0
T1
T2
RD/
D63âD0
(read)
DACKn
(SA: IO â memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.74 Byte Control SRAM Basic Read Cycle (No Wait)
Rev. 6.0, 07/02, page 475 of 986
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese