HD6417750 Datasheet, PDF (665/1039 Pages) Renesas Technology Corp – SuperH RISC engine

15.2.9 Bit Rate Register (SCBRR1)
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
SCBRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SCSMR1.
SCBRR1 can be read or written to by the CPU at all times.
SCBRR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the
module standby state.
The SCBRR1 setting is found from the following equations.
Asynchronous mode:
N=
Pφ
× 10⁶ – 1
64 × 2^2n–1 × B
Synchronous mode:
N=
Pφ
× 10⁶ – 1
8 × 2^2n–1 × B
Where B: Bit rate (bits/s)
N: SCBRR1 setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Peripheral module operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SCSMR1 Setting
n
Clock
CKS1
CKS0
0
Pφ
0
0
1
Pφ/4
0
1
2
Pφ/16
1
0
3
Pφ/64
1
1
Rev. 6.0, 07/02, page 613 of 986