HD6417750 Datasheet, PDF (59/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 1.1 SH7750 Series Features (cont)
Item
Direct memory
access controller
(DMAC)
Features
• Physical address DMA controller:
 SH7750, SH7750S: 4-channel
 SH7750R: 8-channel
• Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes
• Address modes:
 Single address mode
 Dual address mode
• Transfer requests: External, on-chip module, or auto-requests
• Bus modes: Cycle-steal or burst mode
• Supports on-demand data transfer
Timer unit (TMU)
• Auto-reload 32-bit timer:
 SH7750, SH7750S: 3-channel
 SH7750R: 5-channel
• Input capture function
• Choice of seven counter input clocks
Realtime clock
(RTC)
• On-chip clock and calendar functions
• Built-in 32 kHz crystal oscillator with maximum 1/256 second resolution
(cycle interrupts)
Serial
communication
interface
(SCI, SCIF)
• Two full-duplex communication channels (SCI, SCIF)
• Channel 1 (SCI):
 Choice of asynchronous mode or synchronous mode
 Supports smart card interface
• Channel 2 (SCIF):
 Supports asynchronous mode
 Separate 16-byte FIFOs provided for transmitter and receiver
Rev. 6.0, 07/02, page 7 of 986