HD6417750 Datasheet, PDF (154/1039 Pages) Renesas Technology Corp – SuperH RISC engine

• Tag
Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached.
The tag is not initialized by a power-on or manual reset.
• V bit (validity bit)
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
• U bit (dirty bit)
The U bit is set to 1 if data is written to the cache line while the cache is being used in copy-
back mode. That is, the U bit indicates a mismatch between the data in the cache line and the
data in external memory. The U bit is never set to 1 while the cache is being used in write-
through mode, unless it is modified by accessing the memory-mapped cache (see section 4.5,
Memory-Mapped Cache Configuration). The U bit is initialized to 0 by a power-on reset, but
retains its value in a manual reset.
• Data field
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
• LRU (SH7750R only)
In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each
entry address (address: 13–5). When an entry is registered, the LRU bit indicates which of the
2 ways it is to be registered in. The LRU bit is a single bit of each entry, and its value is
controlled by hardware.
The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently
accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset.
The LRU bits cannot be read or written by software.
Rev. 6.0, 07/02, page 102 of 986