HD6417750 Datasheet, PDF (15/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Section
Page
14.2.1 DMA Source Address 496
Registers 0–3 (SAR0–SAR3)
14.2.2 DMA Destination
497
Address Registers 0–3
(DAR0–DAR3)
14.2.3 DMA Transfer Count 498
Registers 0–3 (DMATCR0–
DMATCR3)
14.2.4 DMA Channel Control 499
Registers 0–3 (CHCR0–
CHCR3)
502, 503
503
505
14.2.5 DMA Operation
508
Register (DMAOR)
14.3.2 DMA Transfer
513
Requests
14.3.4 Types of DMA
526
Transfer
525
14.3.5 Number of Bus Cycle 533 to
States and '5(4 Pin
535
Sampling Timing
14.5 On-Demand Data
545
Transfer Mode (DDT Mode)
14.5.2 Pins in DDT Mode 547
14.5.3 Transfer Request
551, 552
Acceptance on Each Channel ₅₅₃
554
554, 555
14.5.4 Notes on Use of DDT 572
Module
573
573
Item
Description
Description amended
Description amended
Description amended
Bits 19 to 16
Bits 15, 14 and Bits 13, 12
Bits 6 to 4
Bit 4
Description of DDT
mode added
Initial value changed
Description amended
Description added
Description amended
• External Request
Acceptance Conditions
Description added
Table 14.9 External Request Usable DMAC channels
Transfer Sources and
changed
Destinations in DDT Mode
(a) Normal DMA Mode
Description amendment
Figure 14.15 to 14.17
Figure description
added
%$9/: Data bus D63–D0
release signal
Figures 14.26, 14.27
Figure 14.28
Figure 14.29
Figure 14.30, 14.31
c. of 3. Handshake protocol
using the data bus (valid on
channel 0 only)
b. of 8. Data transfer end
request
12. Confirming DMA transfer
requests and number of
transfers executed
Description
amendments
Description added
Title amended
Newly added
Amended
Errors corrected
Description amended
Added
Description amended
Rev. 6.0, 07/02, page xiii of I