HD6417750 Datasheet, PDF (61/1039 Pages) Renesas Technology Corp – SuperH RISC engine

1.2 Block Diagram
Figure 1.1 shows an internal block diagram of the SH7750 Series.
CPU
UBC
FPU
Lower 32-bit data
Lower 32-bit data
I cache
Cache and
ITLB
TLB
UTLB
controller
O cache
CPG
INTC
SCI
(SCIF)
RTC
TMU
BSC
DMAC
External
bus interface
26-bit
address
64-bit
data
BSC: Bus state controller
CPG: Clock pulse generator
DMAC: Direct memory access controller
FPU: Floating-point unit
INTC: Interrupt controller
ITLB: Instruction TLB (translation lookaside buffer)
UTLB:
RTC:
SCI:
SCIF:
TMU:
UBC:
Unified TLB (translation lookaside buffer)
Realtime clock
Serial communication interface
Serial communication interface with FIFO
Timer unit
User break controller
Figure 1.1 Block Diagram of SH7750 Series Functions
Rev. 6.0, 07/02, page 9 of 986