HD6417750 Datasheet, PDF (488/1039 Pages) Renesas Technology Corp – SuperH RISC engine

auto-refreshing has been executed at least the prescribed number of times, a mode register setting
command is issued in the TMw1 cycle by setting MCR.MRSET to 1 and performing a write to
address H'FF900000 + X or H'FF940000 + X.
Synchronous DRAM mode register setting should be executed once only after power-on (reset)
and before synchronous DRAM access, and no subsequent changes should be made.
CKIO
TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5
Bank
Precharge-sel
Address
RD/
D31–D0
CKE
(High)
Figure 13.42 (1) Synchronous DRAM Mode Write Timing (PALL)
Rev. 6.0, 07/02, page 436 of 986