HD6417750 Datasheet, PDF (803/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Section 19 Interrupt Controller (INTC)
19.1 Overview
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to handle interrupt requests according to user-set priority.
19.1.1 Features
The INTC has the following features.
• Fifteen interrupt priority levels can be set
By setting the three interrupt priority registers, the priorities of on-chip peripheral module
interrupts can be selected from 15 levels for different request sources.
• NMI noise canceler function
The NMI input level bit indicates the NMI pin state. The pin state can be checked by reading
this bit in the interrupt exception service routine, enabling it to be used as a noise canceler.
• NMI request masking when SR.BL bit is set to 1
It is possible to select whether or not NMI requests are to be masked when the SR.BL bit is set
to 1.
19.1.2 Block Diagram
Figure 19.1 shows a block diagram of the INTC.
Rev. 6.0, 07/02, page 751 of 986