HD6417750 Datasheet, PDF (473/1039 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
Bank
Precharge-sel
Address
Tr Trw Tc1 Tc2 Tc3 Tc4 Trw1 Trw1 Tpc
Row
Row
H/L
Row
c1
RD/
DQMn
D63–D0
c1
(read)
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.31 Basic Timing for Synchronous DRAM Single Write
Rev. 6.0, 07/02, page 421 of 986