HD6417750 Datasheet, PDF (717/1039 Pages) Renesas Technology Corp – SuperH RISC engine

In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2—Reserved: This bit is always read as 0, and should only be written with 0.
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the on-
chip baud rate generator. The clock source can be selected from Pφ, Pφ/4, Pφ/16, and Pφ/64,
according to the setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 16.2.8, Bit Rate Register (SCBRR2).
Bit 1: CKS1 Bit 0: CKS0
0
0
1
1
0
1
Note: Pφ: Peripheral clock
Description
Pφ clock
Pφ/4 clock
Pφ/16 clock
Pφ/64 clock
(Initial value)
16.2.6 Serial Control Register (SCSCR2)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
REIE
—
CKE1
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W
R
R/W
R
The SCSCR2 register performs enabling or disabling of SCIF transfer operations, and interrupt
requests, and selection of the serial clock source.
SCSCR2 can be read or written to by the CPU at all times.
SCSCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Rev. 6.0, 07/02, page 665 of 986