HD6417750 Datasheet, PDF (908/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 22.31 Clock and Control Signal Timing (HD6417750F167, HD6417750F167I,
HD6417750SF167, HD6417750SF167I)
HD6417750SF167, HD6417750F167: V_DDQ = 3.0 to 3.6 V, V_DD = 1.8 V, T_a = –20 to +75°C,
C_L = 30 pF
HD6417750SF167I, HD6417750F167I: V_DDQ = 3.0 to 3.6 V, V_DD = 1.8 V, T_a = –40 to +85°C,
C_L = 30 pF
Item
Symbol Min
EXTAL
PLL2
1/2 divider
f
16
EX
clock input operating operating
frequency
1/2 divider not f_EX
8
operating
PLL2 not 1/2 divider
f
2
EX
operating operating
1/2 divider not f_EX
1
operating
EXTAL clock input cycle time
t
18
EXcyc
EXTAL clock input low-level pulse width t_EXL
3.5
EXTAL clock input high-level pulse width t_EXH
3.5
EXTAL clock input rise time
t_EXr
—
EXTAL clock input fall time
t
—
EXf
CKIO clock PLL2 operating
f
25
OP
output
PLL2 not operating
f
1
OP
CKIO clock output cycle time
t
12
cyc
CKIO clock output low-level pulse width t_CKOL1
1
CKIO clock output high-level pulse width t_CKOH1
1
CKIO clock output rise time
t
—
CKOr
CKIO clock output fall time
t
—
CKOf
CKIO clock output low-level pulse width t_CKOL2
3
CKIO clock output high-level pulse width t_CKOH2
3
Power-on oscillation settling time
t_OSC1
10
Power-on oscillation settling time/mode t_OSCMD
10
settling
SCK2 reset setup time
SCK2 reset hold time
MD reset setup time
MD reset hold time
t
20
SCK2RS
t_SCK2RH
20
t_MDRS
3
t
20
MDRH
Max Unit Figure
56
MHz
28
56
28
1000
—
—
4
4
84
84
1000
—
—
3
3
—
—
—
—
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ms
ms
22.1
22.1
22.1
22.1
22.1
22.2(1)
22.2(1)
22.2(1)
22.2(1)
22.2(1)
22.2(2)
22.2(2)
22.3, 22.5
22.3, 22.5
—
ns 22.11
—
ns 22.3, 22.5, 22.11
—
t_cyc
22.12
—
ns 22.3, 22.5, 22.12
Rev. 6.0, 07/02, page 856 of 986