HD6417750 Datasheet, PDF(1030/1039 Page) Renesas Technology Corp – SuperH RISC engine

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HD6417750 Datasheet, PDF (1030/1039 Pages) Renesas Technology Corp – SuperH RISC engine

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Appendix H Power-On and Power-Off Procedures

â¢ Power-on

ï£§ Supply the internal power after supplying power to the I/O, PLL, RTC, and CPG.*1

ï£§ Supply power to VDDQ, V , DD-PLL1/2 V , DD-RTC and VDD-CPG simultaneously.

ï£§ At power-on, the 5(6(7 signal is low. Normally, supply power to the I/O, RTC, and CPG

before (or at the same time as) entering the signal lines (5(6(7, SCK2, MD0 to MD10,

and external clock). If the signal lines are entered first, the LSI may be damaged.

ï£§ Input high level to SCK2 (05(6(7) in compliance with the voltage level of the I/O, PLL,

RTC, CPG power supply voltage.

â¢ Power-off

ï£§ When turning off the power, there are no restrictions for the timing of 5(6(7 and SCK2.

ï£§ Turn off the I/O, PLL, RTC, CPG power supply voltage after (or at the same time as)*1

turning off the internal power supply voltage.

Note however that the internal power supply voltage may exceed the I/O, PLL, RTC, CPG

power supply voltage by a maximum of 0.3 V only when the system is being turned off.

ï£§ The power supply level must be lowered in compliance with the I/O, PLL, RTC, CPG

power supply voltage.

Note: *1 10 ms or less for the HD6417750R.

â¢ The ratings and procedures for power-on and power-off are given below.

V = V = V = V = V = 0 V SSQ

SS-PLL1

SS-PLL2

SS-RTC

SS-CPG

The LSI may be damaged if

â0.3 V < Vin < VDDQ + 0.3 V

â0.3 V < VDD < VDDQ + 0.3 V

are not satisfied when VDDQ = VDD-RTC = V . DD-CPG

2.0 V

Power-on

1.2 V

GND

ton

0 â¤ ton < 10 ms*

Note: * HD6417750R only

VDDQ

VDD

Power-off

toff

0 â¤ toff < 10 ms*

Figure H.1 Power-On and Power-Off Procedures

Rev. 6.0, 07/02, page 978 of 986

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