HD6417750 Datasheet, PDF (301/1039 Pages) Renesas Technology Corp – SuperH RISC engine

10.2 Overview of CPG
10.2.1 Block Diagram of CPG
Figure 10.1 (1) shows a block diagram of the CPG in the SH7750 and SH7750S, and figure 10.1
(2) a block diagram of the CPG in the SH7750R.
XTAL
EXTAL
MD8
Oscillator circuit
Crystal
oscillator
PLL circuit 1
×6
Frequency
divider 2
×1
× 1/2
× 1/3
× 1/4
× 1/6
× 1/8
Frequency
divider 1
× 1/2
CKIO
PLL circuit 2
×1
CPU clock (Iø)
cycle Icyc
Peripheral module
clock (Pø) cycle
Pcyc
Bus clock (Bø)
cycle Bcyc
MD2
MD1
MD0
CPG control unit
Clock frequency
control circuit
Standby control
circuit
FRQCR
STBCR
Bus interface
STBCR2
FRQCR: Frequency control register
STBCR: Standby control register
STBCR2: Standby control register 2
Internal bus
Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S)
Rev. 6.0, 07/02, page 249 of 986