HD6417750 Datasheet, PDF (797/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 2n (n = 0–3)—Port I/O Control (PBnIO): Specifies whether each bit in the 4-bit port is an
input or an output.
Bit 2n: PBnIO
0
1
Description
Bit m (m = 16–19) of 4-bit port is an input
Bit m (m = 16–19) of 4-bit port is an output
(Initial value)
18.2.4 Port Data Register B (PDTRB)
Port data register B (PDTRB) is a 16-bit readable/writable register used as a data latch for each bit
in the 4-bit port. When a bit is set as an output, the value written to the PDTRB register is output
from the external pin. When a value is read from the PDTRB register while a bit is set as an input,
the external pin value sampled on the external bus clock is read. When a bit is set as an output, the
value written to the PDTRB register is read.
PDTRB is not initialized by a power-on or manual reset, or in standby mode, and retains its
contents.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
— PB19DT PB18DT PB17DT PB16DT
Initial value: 0
0
0
0
—
—
—
—
R/W: R
R
R
R
R/W R/W R/W R/W
18.2.5 GPIO Interrupt Control Register (GPIOIC)
The GPIO interrupt control register (GPIOIC) is a 16-bit readable/writable register that performs
16-bit interrupt input control.
GPIOIC is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or
in standby mode, and retains its contents.
GPIO interrupts are active-low level interrupts. Bit-by-bit masking is possible, and the OR of all
the bits set as GPIO interrupts is used for interrupt detection. Which bits interrupts are input to can
be identified by reading the PDTRA register.
Rev. 6.0, 07/02, page 745 of 986