HD6417750 Datasheet, PDF (475/1039 Pages) Renesas Technology Corp – SuperH RISC engine

that in figure 13.33 or 13.36. In RAS down mode, too, a PALL command is issued before a refresh
cycle or before bus release due to bus arbitration.
CKIO
Bank
Precharge-sel
Address
Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4
Row
Row
H/L
Row
c1
RD/
DQMn
D63–D0
(read)
c1 c2 c3 c4
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.32 Burst Read Timing
Rev. 6.0, 07/02, page 423 of 986