HD6417750 Datasheet, PDF (648/1039 Pages) Renesas Technology Corp – SuperH RISC engine

15.1.3 Pin Configuration
Table 15.1 shows the SCI pin configuration.
Table 15.1 SCI Pins
Pin Name
Serial clock pin
Receive data pin
Transmit data pin
Abbreviation
MD0/SCK
RxD
MD7/TxD
I/O
I/O
Input
Output
Function
Clock input/output
Receive data input
Transmit data output
Note:
The serial clock pin and transmit data pin function as mode input pins MD0 and MD7
after a power-on reset. They are made to function as serial pins by performing SCI
operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR1 and the C/$ bit in
SCSMR1. Break state transmission and detection, can be set in the SCI’s SCSPTR1
register.
15.1.4 Register Configuration
The SCI has the internal registers shown in table 15.2. These registers are used to specify
asynchronous mode or synchronous mode, the data format, and the bit rate, and to perform
transmitter/receiver control.
With the exception of the serial port register, the SCI registers are initialized in standby mode and
in the module standby state as well as after a power-on reset or manual reset. When recovering
from standby mode or the module standby state, the registers must be set again.
Table 15.2 SCI Registers
Name
Abbreviation R/W
Initial
Area 7
Value P4 Address Address
Access
Size
Serial mode register SCSMR1
R/W H'00 H'FFE00000 H'1FE00000 8
Bit rate register
SCBRR1
R/W H'FF H'FFE00004 H'1FE00004 8
Serial control register SCSCR1
R/W H'00 H'FFE00008 H'1FE00008 8
Transmit data register SCTDR1
R/W H'FF H'FFE0000C H'1FE0000C 8
Serial status register SCSSR1
R/(W)*¹ H'84 H'FFE00010 H'1FE00010 8
Receive data register SCRDR1
R
H'00 H'FFE00014 H'1FE00014 8
Serial port register
SCSPTR1
R/W
H'00*² H'FFE0001C H'1FE0001C 8
Notes: *1 Only 0 can be written, to clear flags.
*2 The value of bits 2 and 0 is undefined.
Rev. 6.0, 07/02, page 596 of 986