HD6417750 Datasheet, PDF (275/1039 Pages) Renesas Technology Corp – SuperH RISC engine

9.1.2 Register Configuration
Table 9.2 shows the registers used for power-down mode control.
Table 9.2 Power-Down Mode Registers
Name
Abbreviation R/W
Standby control STBCR
R/W
register
Standby control STBCR2
R/W
register 2
Clock stop
CLKSTP00
R/W
register 00*
Clock release
register 00*
CLKSTPCLR00 W
Note: * SH7750R only
Initial Value
H'00
P4 Address
H'FFC00004
Area 7
Address
H'1FC00004
Access
Size
8
H'00
H'FFC00010 H'1FC00010 8
H'00000000 H'FE0A0000 H'1E0A0000 32
H'00000000 H'FE0A0008 H'1E0A0008 32
9.1.3 Pin Configuration
Table 9.3 shows the pins used for power-down mode control.
Table 9.3 Power-Down Mode Pins
Pin Name
Processor status 1
Processor status 0
Abbreviation
STATUS1
STATUS0
I/O
Output
Hardware standby CA
request
(SH7750S and
SH7750R only)
Notes: H: High level
L: Low level
Input
Function
Indicate the processor’s operating status.
(STATUS1, STATUS0)
HH: Reset
HL: Sleep mode
LH: Standby mode
LL: Normal operation
Transits to hardware standby mode by a
low-level input to the pin.
Rev. 6.0, 07/02, page 223 of 986