HD6417750 Datasheet, PDF (149/1039 Pages) Renesas Technology Corp – SuperH RISC engine

4.2 Register Descriptions
There are three cache and store queue related control registers, as shown in figure 4.1.
CCR
31 30
EMODE*
QACR0
31
16 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0
CB
IIX
ICI ICE OIX ORA OCI WT OCE
54 210
AREA
QACR1
31
54 210
AREA
*: SH7750R only
indicates reserved bits: 0 must be specified in a write; the read value is 0.
Figure 4.1 Cache and Store Queue Control Registers
(1) Cache Control Register (CCR): CCR contains the following bits:
EMODE: Double-sized cache mode (Only for SH7750R; reserved bit for SH7750 and SH7750S)
IIX: IC index enable
ICI: IC invalidation
ICE: IC enable
OIX: OC index enable
ORA: OC RAM enable
OCI: OC invalidation
CB: Copy-back enable
WT: Write-through enable
OCE: OC enable
Longword access to CCR can be performed from H'FF00 001C in the P4 area and H'1F00 001C in
area 7. The CCR bits are used for the cache settings described below. Consequently, CCR
modifications must only be made by a program in the non-cached P2 area. After CCR is updated,
an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least
four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or
U0 area should be located at least eight instructions after the CCR update instruction.
Rev. 6.0, 07/02, page 97 of 986