HD6417750 Datasheet, PDF (46/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Figure 22.30 Synchronous DRAM Normal Write Bus Cycle:
ACT + WRITE Commands, Burst (RCD[1:0] = 01, TRWL[2:0] = 010) ........ 892
Figure 22.31 Synchronous DRAM Normal Write Bus Cycle:
PRE + ACT + WRITE Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001,
TRWL[2:0] = 010) ........................................................................................... 893
Figure 22.32 Synchronous DRAM Normal Write Bus Cycle:
WRITE Command, Burst (TRWL[2:0] = 010) ................................................ 894
Figure 22.33 Synchronous DRAM Bus Cycle:
Synchronous DRAM Precharge Command (TPC[2:0] = 001)......................... 895
Figure 22.34 Synchronous DRAM Bus Cycle:
Synchronous DRAM Auto-Refresh (TRAS = 1, TRC[2:0] = 001).................. 896
Figure 22.35 Synchronous DRAM Bus Cycle:
Synchronous DRAM Self-Refresh (TRC[2:0] = 001)...................................... 897
Figure 22.36 (a) Synchronous DRAM Bus Cycle:
Synchronous DRAM Mode Register Setting (PALL)...................................... 898
Figure 22.36 (b) Synchronous DRAM Bus Cycle:
Synchronous DRAM Mode Register Setting (SET)......................................... 899
Figure 22.37 DRAM Bus Cycles
(1) RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001
(2) RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 010 .................................... 900
Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000,
TPC[2:0] = 001) ............................................................................................... 901
Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000,
TPC[2:0] = 001) ............................................................................................... 902
Figure 22.40 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001,
TPC[2:0] = 001) ............................................................................................... 903
Figure 22.41 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001,
TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width) ....................................... 904
Figure 22.42 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode,
RCD[1:0] = 00, AnW[2:0] = 000).................................................................... 905
Figure 22.43 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode,
RCD[1:0] = 00, AnW[2:0] = 000).................................................................... 906
Figure 22.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00,
AnW[2:0] = 000, TPC[2:0] = 001)................................................................... 907
Figure 22.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01,
AnW[2:0] = 001, TPC[2:0] = 001)................................................................... 908
Figure 22.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01,
AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width)........... 909
Figure 22.47 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode,
RCD[1:0] = 00, AnW[2:0] = 000).................................................................... 910
Figure 22.48 DRAM Burst Bus Cycle: RAS Down Mode Continuation
(Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000) ....................................... 911
Rev. 6.0, 07/02, page xliv of I