HD6417750 Datasheet, PDF (21/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Section
22.3.4 Peripheral Module
Signal Timing
Page
924, 925
900 to
921, 923
930
932
Appendix A Address List
937 to
942
Appendix B Package
Dimensions
943, 944
Appendix C Mode Pin
946
Settings
947
Appendix D &.,25(1% Pin
Configuration
Appendix E Pin Functions
948
950 to
952
Appendix F Synchronous
DRAM Address
Multiplexing Tables
970, 971
Item
Description
Table 22.36 Peripheral
Module Signal Timing (1)
Table newly added
Figures 22.37 to 22.58,
Figure 22.60
Titles amended
Figure 22.62 RTC Oscillation Amended
Settling Time at Power-On
Figure 22.66(b) '%5(4/75 Newly added
Input Timing and %$9/
Output Timing
Table A.1 Address List
BCR4, RCR3, RYRAR,
SDINT and Notes
added
BCR3 area 7 address
amended
DMAC, INTC, CPG,
TMU table added
Figure B.1 Package
Amended
Dimensions (256-Pin BGA)
Figure B.2 Package
Dimensions (208-Pin QFP)
Clock Modes
Table 10.3 (1), (2)
inserted
Area 0 Bus Width
Area 0 memory type
deleted and data
integrated into area 0
bus width table
Figure D.1 &.,25(1% Pin Amended
Configuration
Table E.1 Pin States in
Reset, Power-Down State,
and Bus-Released State
Sleep row deleted
D40–D51 deleted
Notes added
(17) BUS 64
(128M: 4M × 8b × 4) × 8
(SH7750R only)
Newly added
(18) BUS 64
(256M: 4M × 16b × 4) × 4
(SH7750R only)
Rev. 6.0, 07/02, page xix of I