HD6417750 Datasheet, PDF (405/1039 Pages) Renesas Technology Corp – SuperH RISC engine

on reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the
same values should be written to the other bits so that they remain unchanged. When using DRAM
or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is
completed.
Bit: 31
30
29
28
27
26
25
24
Bit name: RASD MRSET TRC2 TRC1 TRC0
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W
R
R
R
Bit: 23
22
21
20
19
18
17
16
Bit name: TCAS
—
TPC2 TPC1 TPC0
—
RCD1 RCD0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R/W R/W R/W
R
R/W R/W
Bit: 15
14
13
12
11
10
9
8
Bit name: TRWL2 TRWL1 TRWL0 TRAS2 TRAS1 TRAS0 BE
SZ1
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Bit name:
Initial value:
R/W:
7
6
5
SZ0 AMXEXT AMX2
0
0
0
R/W R/W R/W
4
AMX1
0
R/W
3
AMX0
0
R/W
2
RFSH
0
R/W
1
RMODE
0
R/W
0
EDO
MODE
0
R/W
Bit 31—RAS Down (RASD): Sets RAS down mode. When DRAM/RAS down mode is used, set
BE to 1. Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3
are both designated as synchronous DRAM interface.
Bit 31: RASD
Description
0
Normal mode
(Initial value)
1
RAS down mode
Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2–DMAIW0 to 000
and bits A3IW2–A3IW0 to 000.
Rev. 6.0, 07/02, page 353 of 986