HD6417750 Datasheet, PDF (896/1039 Pages) Renesas Technology Corp – SuperH RISC engine

22.3.1 Clock and Control Signal Timing
Table 22.25 Clock and Control Signal Timing (HD6417750RBP240)
V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V, T_a = –20 to +75°C, C_L = 30 pF
Item
Symbol Min
EXTAL
PLL1 6-times/PLL2
f
16
EX
clock input operation
frequency _{PLL1 12-times/PLL2}
f
14
EX
operation
PLL1/PLL2 not operating f_EX
1
EXTAL clock input cycle time
t_EXcyc
30
EXTAL clock input low-level pulse width t_EXL
3.5
EXTAL clock input high-level pulse width t
3.5
EXH
EXTAL clock input rise time
t
—
EXr
EXTAL clock input fall time
t
—
EXf
CKIO clock PLL1/PLL2 operating
f
25
OP
output
PLL1/PLL2 not operating f
1
OP
CKIO clock output cycle time
t
8.3
cyc
CKIO clock output low-level pulse width t
1
CKOL1
CKIO clock output high-level pulse width t
1
CKOH1
CKIO clock output rise time
t_CKOr
—
CKIO clock output fall time
t_CKOf
—
CKIO clock output low-level pulse width t_CKOL2
3
CKIO clock output high-level pulse width t_CKOH2
3
Power-on oscillation settling time
t
10
OSC1
Power-on oscillation settling time/mode t
10
OSCMD
settling
SCK2 reset setup time
SCK2 reset hold time
MD reset setup time
MD reset hold time
5(6(7 assert time
t
20
SCK2RS
t
20
SCK2RH
t
3
MDRS
t_MDRH
20
t_RESW
20
PLL synchronization settling time
t
200
PLL
Standby return oscillation settling time 1 t
3
OSC2
Standby return oscillation settling time 2 t
3
OSC3
Max Unit Figure
34
MHz
20
34
1000
—
—
4
4
120
34
1000
—
—
3
3
—
—
—
—
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ms
ms
22.1
22.1
22.1
22.1
22.1
22.2(1)
22.2(1)
22.2(1)
22.2(1)
22.2(1)
22.2(2)
22.2(2)
22.3, 22.5
22.3, 22.5
—
ns 22.11
—
ns 22.3, 22.5, 22.11
—
t
22.12
cyc
—
ns 22.3, 22.5, 22.12
—
t_cyc
22.3, 22.4, 22.5,
22.6, 22.11
—
µs 22.9, 22.10
—
ms 22.4, 22.6
—
ms 22.7
Rev. 6.0, 07/02, page 844 of 986