HD6417750 Datasheet, PDF (296/1039 Pages) Renesas Technology Corp – SuperH RISC engine

9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only)
Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode.
The CA pin level must be kept low while in hardware standby mode.
After setting the 5(6(7 pin level low, the clock starts when the CA pin level is switched to high.
CKIO
CA
SCK2
(High)
STATUS
Normal^*1
Standby^*3
*2
Reset
0–10 Bcyc
Waiting for end of bus cycle
0–10 Bcyc
Notes: *1 Same at sleep and reset.
*2 Undefined
*3 High impedance when STBCR2. STHZ = 0
Figure 9.12 Hardware Standby Mode Timing
(When CA = Low in Normal Operation)
Rev. 6.0, 07/02, page 244 of 986