HD6417750 Datasheet, PDF (386/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 4 to 2—Area 2 and 3 Memory Type (DRAMTP2–DRAMTP0): These bits specify the type
of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as
SRAM interface. DRAM and synchronous DRAM can also be connected.
Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description
0
0
0
Areas 2 and 3 are SRAM interface or
MPX interface*¹
(Initial value)
1
Reserved (Cannot be set)
1
0
Area 2 is SRAM interface or MPX
interface*¹, area 3 is synchronous DRAM
interface
1
Areas 2 and 3 are synchronous DRAM
interface
1
0
0
Area 2 is SRAM interface or MPX
interface*¹, area 3 is DRAM interface
1
Areas 2 and 3 are DRAM interface*²
1
0
Reserved (Cannot be set)
1
Reserved (Cannot be set)
Note:
*1 Selection of SRAM interface or MPX interface is determined by the setting of the
MEMMPX bit
*2 When this mode is selected, 16 or 32 bits should be specified as the bus width for areas
2 and 3. In this mode the MD5 pin is designated for output as the 5$65 pin.
Bit 0—Area 5 and 6 Bus Type (A56PCM): Specifies whether areas 5 and 6 are accessed as
PCMCIA interface. The setting of these bits has priority over the MEMMPX bit settings.
Bit 0: A56PCM
Description
0
Areas 5 and 6 are accessed as SRAM interface
1
Areas 5 and 6 are accessed as PCMCIA interface*
Note: * The MD3 pin is designated for output as the &(5$ pin.
The MD4 pin is designated for output as the &(5% pin.
(Initial value)
Rev. 6.0, 07/02, page 334 of 986