HD6417750 Datasheet, PDF (818/1039 Pages) Renesas Technology Corp – SuperH RISC engine

19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only)
The interrupt mask register 00 (INTMSK00) sets the masking of individual interrupt requests.
INTMSK00 is a 32-bit register. It is initialized to H'000003FF by a reset, and retains this value in
standby mode.
To cancel masking of an interrupt, write a 1 to the corresponding bit in the INTMSKCLR00
register. Note that writing a 0 to a bit in INTMSK00 does not change its value.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 31 to 0—Interrupt Mask: Sets the masking of the interrupt request that corresponds to the
given bit. For the correspondence between bits and interrupt sources, see section 19.3.7, Bit
Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only).
Bits 31 to 0
0
1
Description
Interrupt requests from the source that corresponds to this bit are
accepted
Interrupt requests from the source that corresponds to this bit are
masked
(Initial value)
Rev. 6.0, 07/02, page 766 of 986