HD6417750 Datasheet, PDF (14/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Section
13.3.7 PCMCIA Interface
13.3.8 MPX Interface
13.3.9 Byte Control SRAM
Interface
13.3.10 Waits between
Access Cycles
13.3.11 Bus Arbitration
13.3.16 Notes on Usage
14.1 Overview
14.1.1 Features
14.1.2 Block Diagram
(SH7750, SH7750S)
14.2 Register Descriptions
(SH7750, SH7750S)
Page
Item
Description
444, 445
Description amended
and added
446
Table 13.18 Relationship Table amended
between Address and CE
when Using PCMCIA
Interface
449, 452 Figures 13.50, 13.53 to 13.55 Notes added
to 454
450
Figure 13.51 Wait Timing for SH7750R added to
PCMCIA Memory Card
Note
Interface
451
Figure 13.52 PCMCIA Space Amended
Allocation
455
Description added and
amended
471
Figure 13.71 MPX Interface Amended
Timing 7
457 to 472 Figures 13.57 to 13.72
Notes added
473
Description amended
475 to 477 Figures 13.74 to 13.76
Notes added
479
Figure 13.77 Waits between Replaced
Access Cycles
480, 481
Description added and
amended
487
Refresh, Bus Arbitration
Description amended
487
Synchronous DRAM Mode Newly added
Register Setting (SH7750,
SH7750R Only)
489
Description added and
amended
489 to 491
Description amended
492
Title amended
492
Figure 14.1 Block Diagram Amended
of DMAC
496
Title amended
Rev. 6.0, 07/02, page xii of I