HD6417750 Datasheet, PDF (352/1039 Pages) Renesas Technology Corp – SuperH RISC engine

2. Channel 2 TCR bit configuration
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
ICPF UNF
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
Bit:
Initial value:
R/W:
7
ICPE1
0
R/W
6
ICPE0
0
R/W
5
UNIE
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
3. TCR bit configuration for channels 3 and 4 (SH7750R only)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
UNF
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
—
UNIE
—
0
0
0
R
R/W
R
3
2
1
0
— TPSC2 TPSC1 TPSC0
0
0
0
0
R
R/W R/W R/W
Bits 15 to 9, 7, and 6 (Channels 0 and 1); Bits 15 to 10 (Channel 2)—Reserved: These bits are
always read as 0. A write to these bits is invalid, but the write value should always be 0.
Bit 9—Input Capture Interrupt Flag (ICPF) (Channel 2 Only): Status flag, provided in
channel 2 only, that indicates the occurrence of input capture.
Bit 9: ICPF
Description
0
Input capture has not occurred
[Clearing condition]
When 0 is written to ICPF
1
Input capture has occurred
[Setting condition]
When input capture occurs*
Note: * Writing 1 does not change the value.
(Initial value)
Rev. 6.0, 07/02, page 300 of 986