HD6417750 Datasheet, PDF (651/1039 Pages) Renesas Technology Corp – SuperH RISC engine

15.2.5 Serial Mode Register (SCSMR1)
Bit: 7
6
5
C/$
CHR
PE
Initial value: 0
0
0
R/W: R/W R/W R/W
4
3
2
1
0
O/( STOP MP CKS1 CKS0
0
0
0
0
0
R/W R/W R/W R/W R/W
SCSMR1 is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate
generator clock source.
SCSMR1 can be read or written to by the CPU at all times.
SCSMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Bit 7—Communication Mode (C/$): Selects asynchronous mode or synchronous mode as the
SCI operating mode.
Bit 7: C/$
0
1
Description
Asynchronous mode
Synchronous mode
(Initial value)
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In
synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting,
Bit 6: CHR
Description
0
8-bit data
1
7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of SCTDR1 is not transmitted.
(Initial value)
Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In synchronous mode, parity bit
addition and checking is not performed, regardless of the PE bit setting.
Bit 5: PE
Description
0
Parity bit addition and checking disabled
(Initial value)
1
Parity bit addition and checking enabled*
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/( bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity (even
or odd) specified by the O/( bit.
Rev. 6.0, 07/02, page 599 of 986