HD6417750 Datasheet, PDF (556/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source.
Bit 11: Bit 10: Bit 9: Bit 8:
RS3 RS2 RS1 RS0 Description
0
0
0
0
External request, dual address mode*¹ *⁴ (external address
space → external address space)
(Initial value)
1
Setting prohibited
1
0
External request, single address mode
External address space → external device*¹ *³ *⁴
1
External request, single address mode
External device → external address space*¹ *³ *⁴
1
0
0
Auto-request (external address space → external address
space)*²
1
Auto-request (external address space → on-chip peripheral
module)*²
1
0
Auto-request (on-chip peripheral module → external address
space)*²
1
Setting prohibited
1
0
0
0
SCI transmit-data-empty interrupt transfer request
(external address space → SCTDR1)*²
1
SCI receive-data-full interrupt transfer request
(SCRDR1 → external address space)*²
1
0
SCIF transmit-data-empty interrupt transfer request
(external address space → SCFTDR2)*²
1
SCIF receive-data-full interrupt transfer request
(SCFRDR2 → external address space)*²
1
0
0
TMU channel 2 (input capture interrupt, external address space
→ external address space)*²
1
TMU channel 2 (input capture interrupt, external address space
→ on-chip peripheral module)*²
1
0
TMU channel 2 (input capture interrupt, on-chip peripheral
module → external address space)*²
1
Setting prohibited
Notes: *1 External request specifications are valid only for channels 0 and 1. Requests are not
accepted for channels 2 and 3 in normal DMA mode.
*2 Dual address mode
*3 In DDT mode, selection is possible with the DTR format [60] (R/W bit) and [57-56]
(MD1, MD0 bits) specification for channel 0 only.
*4 In DDT mode:
[SH7750] An external request specification should be set for channels 1 to 3. For
channel 0, only single address mode can be set with the DTR format.
[SH7750S] An external request specification can be set for channels 0 to 3.
Rev. 6.0, 07/02, page 504 of 986