HD6417750 Datasheet, PDF (8/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Section
3.3.3 Virtual Address Space
3.3.4 On-Chip RAM Space
3.3.7 Address Space
Identifier (ASID)
4.1.1 Features
Page
68, 69
69
70
95
95
96
4.2 Register Descriptions 97
97
4.3.1 Configuration
101
4.3.6 RAM Mode
4.3.7 OC Index Mode
4.4.1 Configuration
106 to
107
107
109
110
4.6 Memory-Mapped Cache 116
Configuration (SH7750R)
4.7 Store Queues
122
4.7.3 Transfer to External
Memory
4.7.4 SQ Protection
4.7.5 Reading the SQs
(SH7750R Only)
4.7.6 SQ Usage Notes
5.2 Register Descriptions
5.4 Exception Types and
Priorities
122, 123
124
124
125
128
130 to
132
Item
Description
Description changed
Description changed
Note added
Completely revised
Table 4.1 Cache Features
(SH7750, SH7750S)
Completely revised
Table 4.2 Cache Features
(SH7750R)
Newly added
Table 4.3 Features of Store Description added
Queues
Figure 4.1 Cache and Store Figure changed and
Queue Control Registers
Note added
(1) Cache Control Register Description added and
(CCR)
amended
Description added
Figure 4.3 Configuration of Newly added
Operand Cache (SH7750R)
Description amended
and added
Description added
Figure 4.5 amended to
figure 4.6, description
added and amended
Figure 4.7 Configuration of Newly added
Instruction Cache (SH7750R)
Newly added
Description amended
and added
Description added
Description added
Newly added
Table 5.2 Exceptions
Newly added
Description amended
Description and note
added
Rev. 6.0, 07/02, page vi of I