HD6417750 Datasheet, PDF (390/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 12 to 1—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 0Burst Length (SDBL): Sets the burst length when the synchronous DRAM interface is
used. The burst-length setting is only valid when the bus width is 32 bits.
Bit 0: SDBL
0
1
Description
Burst length is 8
Burst length is 4
(Initial value)
13.2.4 Bus Control Register 4 (BCR4) (SH7750R Only)
Bus control register 4 (BCR4) is a 32-bit readable/writable register that enables asynchronous
input to the pin corresponding to each bit.
BCR4 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or
in standby mode.
When asynchronous input is set (ASYNCn = 1), the sampling timing is one cycle earlier than
when synchronous input is set (ASYNCn = 0)* (see figure 13.4)
The timings shown in this section and section 22, Electrical Characteristics, are all for the case
where synchronous input is set (ASYNCn = 0).
Note: * With the synchronous input setting, ensure that setup and hold times are observed.
T1
Tw
Tw
Twe
T2
CKIO
(BCR4.ASYNC0 = 0)
(BCR4.ASYNC0 = 1)
Figure 13.4 Example of 5'< Sampling Timing at which BCR4 is Set
(Two Wait Cycles are Inserted by WCR2)
Rev. 6.0, 07/02, page 338 of 986