HD6417750 Datasheet, PDF (10/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Section
9.8.5 Hardware Standby
Mode Timing (SH7750S,
SH7750R Only)
10.2.1 Block Diagram of
CPG
Page
244 to
246
249
250
10.2.2 CPG Pin
252
Configuration
10.2.3 CPG Register
252
Configuration
10.3 Clock Operating Modes
253
253
254
10.8.2 Watchdog Timer
261
Control/Status Register
(WTCSR)
10.10 Notes on Board
265
Design
266
11.1.1 Features
267
11.1.2 Block Diagram
268
11.1.3 Pin Configuration
269
11.1.4 Register Configuration 270
Item
Figures 9.12, 9.13, 9.15
Description
Figures changed
Notes added
Figure 10.1 (1) Block
Diagram of CPG (SH7750,
SH7750S)
Figure 10.1 (2) Block
Diagram of CPG (SH7750R)
Table 10.1 CPG Pins
Table 10.2 CPG Register
Amended
Newly added
Table and Note
amended
Description added
Description added and
amended
Table 10.3 (1) Clock
Operating Modes (SH7750,
SH7750S)
Table amended and
Note amended and
added
Table 10.3 (2) Clock
Newly added
Operating Modes (SH7750R)
Table 10.4 FRQCR Settings Table and Note
and Internal Clock
amended
Frequencies
Description amended
When Using a PLL Oscillator Description amended
Circuit
Figure 10.5 Points for
Attention when Using PLL
Oscillator Circuit
Amended
Description added for
Alarm interrupts
Figure 11.1 Block Diagram Figure amended and
of RTC
Note added
Table 11.1 RTC Pins
Table amended
Table 11.2 RTC Registers
RTC control register 3
and Year alarm register
added to table, and
Note added
Rev. 6.0, 07/02, page viii of I