HD6417750 Datasheet, PDF (974/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Figure 22.59 Memory Byte Control SRAM Bus Cycles
(1) Basic Read Cycle (No Wait)
(2) Basic Read Cycle (One Internal Wait)
(3) Basic Read Cycle (One Internal Wait + One External Wait)
Rev. 6.0, 07/02, page 922 of 986