HD6417750 Datasheet, PDF (945/1039 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
BANK
Precharge-sel
Address
RD/
Tpr
Tpc
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Trwl
Trwl
t_AD
Row
H/L
t_AD
Row
Row
t_AD
H/L
Row
c0
t_CSD
t_RWD t_RWD
t_RWD t_RWD
t_RASD t_RASD t_RASD t_RASD
t_CASD2
t_CASD2 t_CASD2
t_AD
t_CSD
DQMn
D63–D0
(write)
t_WDD
t_DQMD
t_DQMD
t_WDD
t_WDD
d0
d1
d2
d3
t_BSD
t_BSD
CKE
DACKn
(SA: IO → memory)
t_DACD
t_DACD
t_DACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE
Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)
Rev. 6.0, 07/02, page 893 of 986