HD6417750 Datasheet, PDF (626/1039 Pages) Renesas Technology Corp – SuperH RISC engine

14.6 Configuration of the DMAC (SH7750R)
14.6.1 Block Diagram of the DMAC
Figure 14.53 is a block diagram of the DMAC in the SH7750R.
On-chip
peripheral
module
TMU
SCI, SCIF
DMAC module
Count control
SARn
Registr control
Activation
control
DARn
DMATCRn
CHCRn
Request
priority
control
DMAOR
queclr0–7
DACK0, DACK1
DRAK0, DRAK1
Bus
interface
dmaqueclr0-7
8
SAR0, DAR0, DMATCR0,
Request CHCR0 only
DDT module
,
DTR command buffer
/
D[63:0]
ID[1:0]
External bus
32B data
buffer
Bus state
controller
DMAORn: DMAC operation register
SARn: DMAC source address register
DARn: DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
n = 0 to 7
DBREQ
DDTMODE
BAVL
DDTD
48 bits
id[2:0]
tdack
Request controller
CH0 CH1 CH2 CH3
CH4 CH5 CH6 CH7
Figure 14.53 Block Diagram of the DMAC
Rev. 6.0, 07/02, page 574 of 986