HD6417750 Datasheet, PDF (313/1039 Pages) Renesas Technology Corp – SuperH RISC engine

10.8.2 Watchdog Timer Control/Status Register (WTCSR)
The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register
containing bits for selecting the count clock and timer mode, and overflow flags.
WTCSR is initialized to H'00 only by a power-on reset via the 5(6(7 pin. It retains its value in
an internal reset due to WDT overflow. When used to count the clock stabilization time when
exiting standby mode, WTCSR retains its value after the counter overflows.
To write to the WTCSR register, use a word-size access with the upper byte set to H'A5. To read
WTCSR, use a byte-size access.
Bit:
Initial value:
R/W:
7
TME
0
R/W
6
WT/,7
0
R/W
5
RSTS
0
R/W
4
WOVF
0
R/W
3
IOVF
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Bit 7—Timer Enable (TME): Specifies starting and stopping of timer operation. Clear this bit to
0 when using the WDT in standby mode or to change a clock frequency.
Bit 7: TME
0
1
Description
Up-count stopped, WTCNT value retained
Up-count started
(Initial value)
Bit 6—Timer Mode Select (WT/,7): Specifies whether the WDT is used as a watchdog timer or
interval timer.
Bit 6: WT/,7
Description
0
Interval timer mode
(Initial value)
1
Watchdog timer mode
Note: The up-count may not be performed correctly if WT/,7 is modified while the WDT is running.
Bit 5—Reset Select (RSTS): Specifies the kind of reset to be performed when WTCNT
overflows in watchdog timer mode. This setting is ignored in interval timer mode.
Bit 5: RSTS
0
1
Description
Power-on reset
Manual reset
(Initial value)
Rev. 6.0, 07/02, page 261 of 986