HD6417750 Datasheet, PDF (23/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Contents
Section 1 Overview........................................................................................................... 1
1.1 SH7750 Series (SH7750, SH7750S, SH7750R) Features ................................................. 1
1.2 Block Diagram .................................................................................................................. 9
1.3 Pin Arrangement ............................................................................................................... 10
1.4 Pin Functions..................................................................................................................... 13
1.4.1 Pin Functions (256-Pin BGA) .............................................................................. 13
1.4.2 Pin Functions (208-Pin QFP) ............................................................................... 23
1.4.3 Pin Functions (264-Pin CSP) ............................................................................... 31
Section 2 Programming Model...................................................................................... 41
2.1 Data Formats ..................................................................................................................... 41
2.2 Register Configuration ...................................................................................................... 42
2.2.1 Privileged Mode and Banks ................................................................................. 42
2.2.2 General Registers ................................................................................................. 45
2.2.3 Floating-Point Registers ....................................................................................... 47
2.2.4 Control Registers.................................................................................................. 49
2.2.5 System Registers .................................................................................................. 50
2.3 Memory-Mapped Registers ............................................................................................... 52
2.4 Data Format in Registers ................................................................................................... 53
2.5 Data Formats in Memory .................................................................................................. 53
2.6 Processor States................................................................................................................. 54
2.7 Processor Modes ............................................................................................................... 55
Section 3 Memory Management Unit (MMU) ......................................................... 57
3.1 Overview ........................................................................................................................... 57
3.1.1 Features ................................................................................................................ 57
3.1.2 Role of the MMU ................................................................................................. 57
3.1.3 Register Configuration ......................................................................................... 60
3.1.4 Caution ................................................................................................................. 60
3.2 Register Descriptions ........................................................................................................ 61
3.3 Address Space ................................................................................................................... 64
3.3.1 Physical Address Space........................................................................................ 64
3.3.2 External Memory Space ....................................................................................... 67
3.3.3 Virtual Address Space.......................................................................................... 68
3.3.4 On-Chip RAM Space ........................................................................................... 69
3.3.5 Address Translation.............................................................................................. 69
3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode.................... 70
3.3.7 Address Space Identifier (ASID) ......................................................................... 70
3.4 TLB Functions................................................................................................................... 71
Rev. 6.0, 07/02, page xxi of I