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HD6417750 Datasheet, PDF (55/1039 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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Table 1.1 SH7750 Series Features (cont)
Item
FPU
Features
⢠On-chip floating-point coprocessor
⢠Supports single-precision (32 bits) and double-precision (64 bits)
⢠Supports IEEE754-compliant data types and exceptions
⢠Two rounding modes: Round to Nearest and Round to Zero
⢠Handling of denormalized numbers: Truncation to zero or interrupt
generation for compliance with IEEE754
⢠Floating-point registers: 32 bits à 16 words à 2 banks
(single-precision à 16 words or double-precision à 8 words) à 2 banks
⢠32-bit CPU-FPU floating-point communication register (FPUL)
⢠Supports FMAC (multiply-and-accumulate) instruction
⢠Supports FDIV (divide) and FSQRT (square root) instructions
⢠Supports FLDI0/FLDI1 (load constant 0/1) instructions
⢠Instruction execution times
 Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8
cycles (double-precision)
 Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles
(double-precision)
Note: FMAC is supported for single-precision only.
⢠3-D graphics instructions (single-precision only):
 4-dimensional vector conversion and matrix operations (FTRV): 4
cycles (pitch), 7 cycles (latency)
 4-dimensional vector inner product (FIPR): 1 cycle (pitch), 4 cycles
(latency)
Rev. 6.0, 07/02, page 3 of 986
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