HD6417750 Datasheet, PDF (243/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 7.12 Floating-Point Graphics Acceleration Instructions
Instruction
FMOV DRm,XDn
FMOV XDm,DRn
FMOV XDm,XDn
FMOV @Rm,XDn
FMOV @Rm+,XDn
FMOV @(R0,Rm),XDn
FMOV XDm,@Rn
FMOV XDm,@-Rn
FMOV XDm,@(R0,Rn)
FIPR FVm,FVn
FTRV XMTRX,FVn
FRCHG
FSCHG
Operation
Instruction Code
Privileged T Bit
DRm → XDn
1111nnn1mmm01100 —
—
XDm → DRn
1111nnn0mmm11100 —
—
XDm → XDn
1111nnn1mmm11100 —
—
(Rm) → XDn
1111nnn1mmmm1000 —
—
(Rm) → XDn, Rm + 8 → Rm 1111nnn1mmmm1001 —
—
(R0 + Rm) → XDn
1111nnn1mmmm0110 —
—
XDm → (Rn)
1111nnnnmmm11010 —
—
Rn – 8 → Rn, XDm → (Rn)
1111nnnnmmm11011 —
—
XDm → (R0+Rn)
1111nnnnmmm10111 —
—
inner_product [FVm, FVn] → 1111nnmm11101101 —
—
FR[n+3]
transform_vector [XMTRX, FVn] 1111nn0111111101 —
—
→ FVn
~FPSCR.FR → SPFCR.FR 1111101111111101 —
—
~FPSCR.SZ → SPFCR.SZ 1111001111111101 —
—
Rev. 6.0, 07/02, page 191 of 986