HD6417750 Datasheet, PDF (937/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Figure 22.23 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single
(RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011)
Rev. 6.0, 07/02, page 885 of 986