HD6417750 Datasheet, PDF (812/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 19.5 Interrupt Exception Handling Sources and Priority Order (cont)
Interrupt Source
INTEVT Interrupt Priority IPR (Bit
Code (Initial Value) Numbers)
Priority within
IPR Setting Unit
TMU3 TUNI3*²
H'B00 15–0 (0)
INTPRI00
—
(11–8)
TMU4 TUNI4*²
H'B80 15–0 (0)
INTPRI00
—
(15–12)
TMU0 TUNI0
H'400 15–0 (0)
IPRA (15–12) —
TMU1 TUNI1
H'420 15–0 (0)
IPRA (11–8) —
TMU2 TUNI2
H'440 15–0 (0)
IPRA (7–4) High
TICPI2
H'460
Low
RTC
ATI
PRI
CUI
H'480
H'4A0
H'4C0
15–0 (0)
IPRA (3–0)
High
↑↓
Low
SCI1 ERI
RXI
TXI
TEI
H'4E0
H'500
H'520
H'540
15–0 (0)
IPRB (7–4)
High
↑

↓
Low
SCIF ERI
RXI
BRI
TXI
H'700
H'720
H'740
H'760
15–0 (0)
IPRC (7–4)
High
↑


↓
Low
WDT ITI
H'560 15–0 (0)
IPRB (15–12) —
REF
RCMI
H'580 15–0 (0)
IPRB (11–8) High
ROVI
H'5A0
Low
Notes: TUNI0–TUNI4: Underflow interrupts
TICPI2: Input capture interrupt
ATI: Alarm interrupt
PRI: Periodic interrupt
CUI: Carry-up interrupt
ERI: Receive-error interrupt
RXI: Receive-data-full interrupt
TXI: Transmit-data-empty interrupt
TEI: Transmit-end interrupt
BRI: Break interrupt request
ITI: Interval timer interrupt
RCMI: Compare-match interrupt
ROVI: Refresh counter overflow interrupt
Default
Priority
High
↑




































↓
Low
Rev. 6.0, 07/02, page 760 of 986