HD6417750 Datasheet, PDF (804/1039 Pages) Renesas Technology Corp – SuperH RISC engine

NMI
–
Input control
4
4
TMU
RTC
SCI
SCIF
WDT
REF
DMAC
H-UDI
GPIO
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Priority
identifier
IPR
ICR
IPRA–IPRD^*1
INTPRI00^*2
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
Bus interface
TMU: Timer unit
RTC: Realtime clock unit
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
WDT: Watchdog timer
REF: Memory refresh controller section of the bus state controller
DMAC: Direct memory access controller
H-UDI: Hitachi user debug interface
GPIO: I/O port
ICR: Interrupt control register
IPRA–IPRD: Interrupt priority registers A–D^*1
INTPRI00: Interrupt priority level setting register 00^*2
SR: Status register
Notes: *1 IPRD is provided only in the SH7750S and SH7750R.
*2 INTPRI00 is provided only in the SH7750R.
INTC
Figure 19.1 Block Diagram of INTC
Rev. 6.0, 07/02, page 752 of 986