HD6417750 Datasheet, PDF (286/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Bit
Description
CSTP1*⁶
0
Peripheral clock is supplied to TMU channels 3 and 4
1
Peripheral clock supplied to TMU channels 3 and 4 is stopped
CSTP0*⁶
0
INTC detects interrupts on TMU channels 3 and 4
1
INTC does not detect interrupts on TMU channels 3 and 4
MSTP6*⁴
0
SQ operates
1
Clock supplied to SQ is stopped
MSTP5*⁴
0
UBC operates
1
Clock supplied to UBC is stopped*⁵
MSTP4
0
DMAC operates
1
Clock supplied to DMAC is stopped*³
MSTP3
0
SCIF operates
1
Clock supplied to SCIF is stopped
MSTP2
0
TMU operates
1
Clock supplied to TMU is stopped, and register is initialized*¹
MSTP1
0
RTC operates
1
Clock supplied to RTC is stopped*²
MSTP0
0
SCI operates
1
Clock supplied to SCI is stopped
Notes: *1 The register initialized is the same as in standby mode, but initialization is not
performed if the RTC clock is not in use (see section 12, Timer Unit (TMU)).
*2 The counter operates when the START bit in RCR2 is 1 (see section 11, Realtime
Clock (RTC)).
*3 Terminate DMA transfers prior to making the transition to module standby mode. If you
make a transition to module standby mode while DMA transfers are in progress, the
results of those transfers cannot be guaranteed.
*4 SH7750S, SH7750R only
*5 For details, see section 20.6, User Break Controller Stop Functions.
*6 SH7750R only
9.6.2 Exit from Module Standby Function
The module standby function is exited by clearing the MSTP6–MSTP0, CSTP1, and CSTP0 bits
to 0, or by a power-on reset via the 5(6(7 pin or a power-on reset caused by watchdog timer
overflow.
Rev. 6.0, 07/02, page 234 of 986