HD6417750 Datasheet, PDF (572/1039 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
A28–A0
CSn
D63–D0
DACK
WE
Address output to external memory
space
Data output from external device
with DACK
DACK signal to external
device with DACK
signal to external memory space
(a) From external device with DACK to external memory space
CKIO
A28–A0
CSn
D63–D0
RD
DACK
Address output to external memory
space
Data output from external memory
space
signal to external memory space
DACK signal to external
device with DACK
(b) From external memory space to external device with DACK
Figure 14.6 DMA Transfer Timing in Single Address Mode
Dual Address Mode: Dual address mode is used to access both the transfer source and the
transfer destination by address. The transfer source and destination can be accessed by either on-
chip peripheral module or external address.
Even if the operand cache is used in RAM mode, the RAM cannot be set as the transfer source or
transfer destination.
In dual address mode, data corresponding to the size specified by CHCRn.TS is read from the
transfer source in the data read cycle, and, in the data write cycle, it is transferred in two bus
cycles in order to write in the transfer destination the data corresponding to the size specified by
Rev. 6.0, 07/02, page 520 of 986