HD6417750 Datasheet, PDF (401/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 5 to 3—Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait
states to be inserted for area 0. For details on MPX interface setting, see table 13.6, MPX Interface
is Selected (Areas 0 to 6).
Bit 5: A0W2
0
1
Bit 4: A0W1
0
1
0
1
Bit 3: A0W0
0
1
0
1
0
1
0
1
Description
First Cycle
Inserted Wait States 5'< Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
6
Enabled
9
Enabled
12
Enabled
15 (Initial value)
Enabled
Bits 2 to 0—Area 0 Burst Pitch (A0B2–A0B0): These bits specify the number of wait states to
be inserted afterwards the second data access in a burst transfer with the burst ROM interface
selected.
Bit 2: A0B2
0
1
Bit 1: A0B1
0
1
0
1
Bit 0: A0B0
0
1
0
1
0
1
0
1
Description
Burst Cycle (Excluding First Cycle)
Wait States Inserted from
Second Data Access Onward 5'< Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
4
Enabled
5
Enabled
6
Enabled
7 (Initial value)
Enabled
Rev. 6.0, 07/02, page 349 of 986