HD6417750 Datasheet, PDF (918/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Stable input clock
EXTAL input
PLL output,
CKIO output
PLL synchronization
Internal clock
Reset or NMI
interrupt request
Stable input clock
t_PLL × 2
PLL synchronization
STATUS1–
STATUS0
Normal
Standby
Normal
Note: When external clock from EXTAL is input
Figure 22.9 PLL Synchronization Settling Time in Case of 5(6(7 or NMI Interrupt
Stable input clock
–
interrupt request
Stable input clock
EXTAL input
PLL output,
CKIO output
PLL synchronization
t_IRLSTB
t_PLL × 2 PLL synchronization
Internal clock
STATUS1–
STATUS0
Normal
Standby
Normal
Note: When external clock from EXTAL is input
Figure 22.10 PLL Synchronization Settling Time in Case of IRL Interrupt
Rev. 6.0, 07/02, page 866 of 986