HD6417750 Datasheet, PDF (555/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or
active-low.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is
invalid.
Bit 16: AL
0
1
Description
Active-high output
Active-low output
(Initial value)
Bits 15 and 14—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify
incrementing/decrementing of the DMA transfer destination address. The specification of these
bits is ignored when data is transferred from external memory to an external device in single
address mode. For channel 0, in DDT mode these bits are set to DM1 = 0 and DM0 = 1 with the
DTR format.
Bit 15: DM1
0
1
Bit 14: DM0
0
1
0
1
Description
Destination address fixed
(Initial value)
Destination address incremented (+1 in 8-bit transfer, +2 in 16-
bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32-
byte burst transfer)
Destination address decremented (–1 in 8-bit transfer, –2 in 16-
bit transfer, –4 in 32-bit transfer, –8 in 64-bit transfer, –32 in 32-
byte burst transfer)
Setting prohibited
Bits 13 and 12—Source Address Mode 1 and 0 (SM1, SM0): These bits specify
incrementing/decrementing of the DMA transfer source address. The specification of these bits is
ignored when data is transferred from an external device to external memory in single address
mode. For channel 0, in DDT mode these bits are set to DM1 = 0 and DM0 = 1 with the DTR
format.
Bit 13: SM1
0
1
Bit 12: SM0
0
1
0
1
Description
Source address fixed
(Initial value)
Source address incremented (+1 in 8-bit transfer, +2 in 16-bit
transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32-
byte burst transfer)
Source address decremented (–1 in 8-bit transfer, –2 in 16-bit
transfer, –4 in 32-bit transfer, –8 in 64-bit transfer, –32 in 32-
byte burst transfer)
Setting prohibited
Rev. 6.0, 07/02, page 503 of 986